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general description the max16060/max16061/max16062 are 1% accurate,quad-/hex-/octal-voltage ? supervisors in a small thin qfn package. these devices provide supervisory func- tions for complex multivoltage systems. the max16060 monitors four voltages, the max16061 monitors six volt- ages, and the max16062 monitors eight voltages. these devices offer independent outputs for each mon- itored voltage along with a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds (down to 0.4v) or the manual reset input is asserted. the reset output remains assert- ed for the reset timeout after all voltages are above their respective thresholds and the manual reset input is deasserted. the minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. all open-drain outputs have internal 30? pullups that eliminate the need for external pullup resistors. however, each output can be driven with an external voltage up to 5.5v. other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. an additional feature is a watchdog timer that asserts reset when the watchdog timeout period (1.6s typ) is exceeded. the watchdog timer can be disabled byleaving wdi unconnected. these devices are offered in 16-, 20-, and 24-pin thin qfn packages (4mm x 4mm) and are fully specified from -40 c to +125 c. features ? fixed thresholds for 3.3v, 2.5v, and 1.8v systems ? adjustable thresholds monitor low voltages(down to 0.4v) ? 1% accurate over temperature ? open-drain outputs with internal pullups reducethe number of external components ? fixed 140ms (min) or capacitor-adjustable resettimeout ? manual reset, margin enable, and toleranceselect inputs ? watchdog timer 1.6s (typ) timeout period54s startup delay after reset ? monitors four (max16060), six (max16061), oreight (max16062) voltages ? reset output indicates all voltages present ? independent voltage monitors ? guaranteed to remain asserted down to v cc = 1v ? small (4mm x 4mm) thin qfn package max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ maxim integrated products 1 max16061a gnd p tol v cc srt mr in1 margin v in1 v in2 v in3 v in4 v in5 v in6 reset wdi out1 rsti/o in2in3 in4 in5 in6 out2 out3 out4 out5 out6 ordering information typical operating circuit 19-4099; rev 0; 4/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. note: the ??is a placeholder for the input voltage threshold. see table 1. the max16060/max16061/max16062 are avail- able in factory-preset thresholds/configuration combinations. choose the desired combination and complete part number from table 1. + denotes a lead-free package. for tape-and-reel, add a ??after the ?.?tape-and-reel are offered in 2.5k increments. * ep = exposed pad. part temp range pin-package max16060 _te+ -40 c to +125 c 16 tqfn-ep* max16061 _tp+ -40 c to +125 c 20 tqfn-ep* max16062 _tg+ -40 c to +125 c 24 tqfn-ep* storage equipmentservers networking/telecommun- ication equipment multivoltage asicsautomotive applications downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 2 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ absolute maximum ratings electrical characteristics(v cc = 2.0v to 5.5v, t a = -40? to +125?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , out_, in_, reset to gnd ..............................-0.3v to +6v tol, margin , mr , srt, wdi to gnd ...........-0.3v to v cc + 0.3 input/output current ( reset , margin , srt, mr , tol, out_, wdi).........................................?0ma continuous power dissipation (t a = +70?) 16-pin tqfn (derate 16.9mw/? above +70?) ......1349mw 20-pin tqfn (derate 16.9mw/? above +70?) ......1355mw 24-pin tqfn (derate 16.9mw/? above +70?) ......1666mw operating temperature range .........................-40? to +125? junction temperature .....................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating voltage range v cc (note 2) 1.0 5.5 v v cc = 3.3v, out_, reset not asserted 45 65 supply current (note 3) i cc v cc = 5v, out_, reset not asserted 50 70 ? uvlo (undervoltage lockout) v uvlo v cc rising 1.62 1.80 1.98 v uvlo hysteresis v uvlo_hys 65 mv in_ (see table 1) 3.3v threshold, tol = gnd 3.069 3.102 3.135 3.3v threshold, tol = v cc 2.904 2.937 2.970 2.5v threshold, tol = gnd 2.325 2.350 2.375 2.5v threshold, tol = v cc 2.200 2.225 2.250 1.8v threshold, tol = gnd 1.674 1.692 1.710 threshold voltages (in_ falling) v th 1.8v threshold, tol = v cc 1.584 1.602 1.620 v tol = gnd 0.390 0.394 0.398 adjustable threshold(in_ falling) v th tol = v cc 0.369 0.373 0.377 v in_ hysteresis v th _ hys in_ rising 0.5 % v th fixed thresholds 3 16 ? in_ input current adjustable thresholds -100 +100 na downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3 electrical characteristics (continued)(v cc = 2.0v to 5.5v, t a = -40? to +125?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units reset srt = v cc 140 200 280 c srt = 1500pf (note 4) 2.43 3.09 3.92 c srt = 100pf 0.206 ms reset timeout t rp c srt = open 50 ? srt ramp current i srt v srt = 0v 460 600 740 na srt threshold 1.173 1.235 1.293 v srt hysteresis 100 mv in_ to reset delay t rd in_ falling 20 ? v c c = 3.3v , i s in k = 10m a, reset asser ted 0.3 v cc = 2.5v, i sink = 6ma, reset asser ted 0.3 reset output-voltage low v ol v cc = 1.2v, i sink = 50?, reset asser ted 0.3 v reset output-voltage high v oh v cc 2.0v, i source = 6?, reset deasserted 0.8 x v cc v mr input-voltage low v il 0.3 x v cc v mr input-voltage high v ih 0.7 x v cc v mr minimum pulse width 1 s mr glitch rejection 100 ns mr to reset delay 200 ns mr pullup resistance pulled up to v cc 12 20 28 k outputs (out_ ) v cc = 3.3v, i sink = 2ma 0.3 out_ output-voltage low v ol v cc = 2.5v, i sink = 1.2ma 0.3 v out_ output-voltage high v oh v cc 2.0v, i source = 6? 0.8 x v cc v in_ to out_ propagation delay t d (v th + 100mv) to (v th - 100mv) 20 ? downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ parameter symbol conditions min typ max units watchdog timer wdi input-voltage low v il 0.3 x v cc v wdi input-voltage high v ih 0.7 x v cc v wdi pulse width (note 5) 50 ns watchdog timeout period t wdi 1.12 1.60 2.40 s watchdog startup period 35 54 72 s watchdog input current v wdi = 0 to v cc (note 5) -1 +1 ? digital logic tol input-voltage low v il 0.3 x v cc v tol input-voltage high v ih 0.7 x v cc v tol input current tol = v cc 100 na margin input-voltage low v il 0.3 x v cc v margin input-voltage high v ih 0.7 x v cc v margin pullup resistance pulled up to v cc 12 20 28 k margin delay time t md rising or falling (note 6) 50 ? electrical characteristics (continued)(v cc = 2.0v to 5.5v, t a = -40? to +125?, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25?). (note 1) note 1: devices are tested at t a = +25? and guaranteed by design for t a = t min to t max . note 2: the outputs are guaranteed to remain asserted down to v cc = 1v. note 3: measured with wdi, margin , and mr unconnected. note 4: the minimum and maximum specifications for this parameter are guaranteed by using the worst case of the srt ramp cur- rent and srt threshold specifications. note 5: guaranteed by design and not production tested. note 6: amount of time required for logic to lock/unlock outputs from margin testing. downloaded from: http:///
typical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage supply voltage (v) supply current ( a) max16060/1/2 toc01 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 30 35 40 45 50 55 60 wdi, margin, and mr unconnected supply current vs. temperature temperature ( c) supply current ( a) max16060/1/2 toc02 -40 -25 -10 5 20 35 50 65 80 95 110 125 30 35 40 45 50 55 60 wdi, margin, and mr unconnected v cc = 2.5v v cc = 3.3v v cc = 5v normalized threshold vs. supply voltage supply voltage (v) normalized threshold max16060/1/2 toc03 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.9900 0.9925 0.9950 0.9975 1.0000 1.0025 1.0050 1.0075 1.0100 normalized threshold vs. temperature temperature ( c) normalized threshold max16060/1/2 toc04 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.995 0.996 0.997 0.998 0.999 1.000 1.001 output voltage vs. sink current sink current (ma) v out _ (mv) max16060/1/2 toc05 012345678 0 25 50 75 100 out_ low output voltage vs. source current source current ( a) v cc - v out_ (mv) max16060/1/2 toc06 0 5 10 15 20 25 30 0 200 400 600 800 1000 out_ high reset timeout period vs. temperature temperature ( c) reset timeout period (ms) max16060/1/2 toc08 -40 -25 -10 5 20 35 50 65 80 95 110 125 190 191 192 193 194 195 196 197 198 1 10 100 1000 maximum transient duration vs. input overdrive max16060/1/2 toc07 input overdrive (mv) maximum transient duration ( s) 600 0 100 200 300 400 500 output goes lowabove this line reset timeout delay max16060/1/2 toc09 out12v/div in15v/div 40ms/div reset2v/div srt = v cc max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _______________________________________________________________________________________ 5 downloaded from: http:///
typical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.) margin disable function max16060/1/2 toc13 out_2v/div margin2v/div 100 s/div reset2v/div out_ and reset are below respectivethresholds watchdog timeout period vs. temperature temperature ( c) watchdog timeout period (s) max16060/1/2 toc11 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.50 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59 1.60 margin enable function max16060/1/2 toc12 out_2v/div margin2v/div 100 s/div reset2v/div out_ and reset arebelow respective thresholds 1000 0.01 0.1 1 10 100 1000 100 10 1 0.1 0.01 reset timeout period vs. c srt max16060/1/2 toc10 c srt (nf) t rp (ms) max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 6 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 7 pin description (max16060) pin name function 1 in3 monitored input voltage 3. see table 1 for the input voltage threshold. 2 in4 monitored input voltage 4. see table 1 for the input voltage threshold. 3 wdi watchdog timer input. if wdi remains low or high for longer than the watchdog timeout period, reset is asserted. the timer clears whenever a reset is asserted or a rising or falling edge on wdi is detected.the watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. leave wdi unconnected to disable the watchdog timer. the wdi unconnected-state detector uses a small 400na current. therefore, do not connect wdi to anything that will source or sink more than 200na. note that the leakage current specification for most three-state drivers exceeds 200na. 4 gnd ground 5v cc unmonitored power-supply input 6 out3 o utp ut 3. when the vol tag e at in 3 fal l s b el ow i ts thr eshol d , ou t3 g oes l ow and stays l ow unti l the vol tag e at in 3 exceed s i ts thr eshol d . the op en- d r ai n outp ut has a 30a i nter nal p ul l up to v c c . 7 out4 o utp ut 4. when the vol tag e at in 4 fal l s b el ow i ts thr eshol d , ou t4 g oes l ow and stays l ow unti l the vol tag e at in 4 exceed s i ts thr eshol d . the op en- d r ai n outp ut has a 30a i nter nal p ul l up to v c c . 8 mr active-low manual reset input. pull mr low to assert reset low. reset remains low for the reset timeout period after mr is deasserted. mr is pulled up to v cc through a 20k resistor. 9 srt set reset timeout input. connect a capacitor from srt to gnd to set the reset timeout period. the resettimeout period can be calculated as follows: reset timeout (s) = 2.06 x 10 6 ( ) x c srt (f). for the internal timeout period of 140ms (min), connect srt to v cc . 10 margin active-low manual deassert input. pull margin low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. 11 out2 o utp ut 2. when the vol tag e at in 2 fal l s b el ow i ts thr eshol d , ou t2 g oes l ow and stays l ow unti l the vol tag e at in 2 exceed s i ts thr eshol d . the op en- d r ai n outp ut has a 30a i nter nal p ul l up to v c c . 12 out1 o utp ut 1. when the vol tag e at in 1 fal l s b el ow i ts thr eshol d , ou t1 g oes l ow and stays l ow unti l the vol tag e at in 1 exceed s i ts thr eshol d . the op en- d r ai n outp ut has a 30a i nter nal p ul l up to v c c . 13 reset active-low reset output. reset asserts low when any of the monitored voltages falls below its respective threshold or mr is asserted. reset remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and mr is deasserted. this open-drain output has a 30? internal pullup. 14 in1 monitored input voltage 1. see table 1 for the input voltage threshold. 15 in2 monitored input voltage 2. see table 1 for the input voltage threshold. 16 tol threshold tolerance input. connect tol to gnd to select 5% threshold tolerance. connect tol to v cc to select 10% threshold tolerance. ? p exposed pad. ep is internally connected to gnd. connect ep to the ground plane to provide a lowthermal resistance path from the ic junction to the pcb. do not use as the electrical connection to gnd. downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 8 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ pin description (max16061) pin name function 1 in4 monitored input voltage 4. see table 1 for the input voltage threshold. 2 in5 monitored input voltage 5. see table 1 for the input voltage threshold. 3 in6 monitored input voltage 6. see table 1 for the input voltage threshold. 4 wdi watchdog timer input. if wdi remains low or high for longer than the watchdog timeout period, reset is asserted and the timer is cleared. the timer also clears whenever a reset is asserted or a rising or fallingedge on wdi is detected. the watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. leave wdi unconnected to disable the watchdog timer. the wdi unconnected-state detector uses a small 400na current. therefore, do not connect wdi to anything that will source or sink more than 200na. note that the leakage current specification for most three-state drivers exceeds 200na. 5 gnd ground 6v cc unmonitored power-supply input 7 out4 output 4. when the voltage at in4 falls below its threshold, out4 goes low and stays low until the voltage atin4 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 8 out5 output 5. when the voltage at in5 falls below its threshold, out5 goes low and stays low until the voltage atin5 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 9 out6 output 6. when the voltage at in6 falls below its threshold, out6 goes low and stays low until the voltage atin6 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 10 mr active-low manual reset input. pull mr low to assert reset low. reset remains low for the reset timeout period after mr is deasserted. mr is pulled up to v cc through a 20k resistor. 11 srt set reset timeout input. connect a capacitor from srt to gnd to set the reset timeout period. the resettimeout period can be calculated as follows: reset timeout (s) = 2.06 x 10 6 ( ) x c srt (f). for the internal timeout period of 140ms (min), connect srt to v cc . 12 margin manual deassert input. pull margin low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. 13 out3 output 3. when the voltage at in3 falls below its threshold, out3 goes low and stays low until the voltage atin3 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 14 out2 output 2. when the voltage at in2 falls below its threshold, out2 goes low and stays low until the voltage atin2 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 15 out1 output 1. when the voltage at in1 falls below its threshold, out1 goes low and stays low until the voltage atin1 exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 16 reset active-low reset output. reset asserts low when any of the monitored voltages falls below its respective threshold or mr is asserted. reset remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and mr is deasserted. this open-drain output has a 30? internal pullup. 17 in1 monitored input voltage 1. see table 1 for the input voltage threshold. 18 in2 monitored input voltage 2. see table 1 for the input voltage threshold. 19 in3 monitored input voltage 3. see table 1 for the input voltage threshold. 20 tol threshold tolerance input. connect tol to gnd to select 5% threshold tolerance. connect tol to v cc to select 10% threshold tolerance. ? p exposed pad. ep is internally connected to gnd. connect ep to the ground plane to provide a low thermalresistance path from the ic junction to the pcb. do not use as the electrical connection to gnd. downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 9 pin name function 1 in5 monitored input voltage 5. see table 1 for the input voltage threshold. 2 in6 monitored input voltage 6. see table 1 for the input voltage threshold. 3 in7 monitored input voltage 7. see table 1 for the input voltage threshold. 4 in8 monitored input voltage 8. see table 1 for the input voltage threshold. 5 wdi watchdog timer input. if wdi remains low or high for longer than the watchdog timeout period, reset is asserted and the timer is cleared. the timer also clears whenever a reset is asserted or a rising or falling edge onwdi is detected. the watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset. leave wdi unconnected to disable the watchdog timer. the wdi unconnected state detector uses a small 400na current. therefore, do not connect wdi to anything that will source or sink more than 200na. note that the leakage current specification for most three-state drivers exceeds 200na. 6 gnd ground 7v cc unmonitored power-supply input 8 out5 output 5. when the voltage at in5 falls below its threshold, out5 goes low and stays low until the voltage at in5exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 9 out6 output 6. when the voltage at in6 falls below its threshold, out6 goes low and stays low until the voltage at in6exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 10 out7 output 7. when the voltage at in7 falls below its threshold, out7 goes low and stays low until the voltage at in7exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 11 out8 output 8. when the voltage at in8 falls below its threshold, out8 goes low and stays low until the voltage at in8exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 12 mr active-low manual reset input. pull mr low to assert reset low. reset remains low for the reset timeout period after mr is deasserted. mr is pulled up to v cc through a 20k resistor. 13 srt set reset timeout input. connect a capacitor from srt to gnd to set the reset timeout period. the reset timeoutperiod can be calculated as follows: reset ti m eout ( s) = 2.06 x 10 6 ( ) x c s rt ( f) . for the i nter nal ti m eout p er i od of 140m s ( m i n) , connect s rt to v c c . 14 margin margin disable input. pull margin low to deassert all outputs (go into high state), regardless of the voltage at any monitored input. 15 out4 output 4. when the voltage at in4 falls below its threshold, out4 goes low and stays low until the voltage at in4exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 16 out3 output 3. when the voltage at in3 falls below its threshold, out3 goes low and stays low until the voltage at in3exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 17 out2 output 2. when the voltage at in2 falls below its threshold, out2 goes low and stays low until the voltage at in2exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 18 out1 output 1. when the voltage at in1 falls below its threshold, out1 goes low and stays low until the voltage at in1exceeds its threshold. the open-drain output has a 30? internal pullup to v cc . 19 reset active-low reset output. reset asserts low when any of the monitored voltages falls below its respective threshold or mr is asserted. reset remains asserted for the reset timeout period after all monitored voltages exceed their respective thresholds and mr is deasserted. this open-drain output has a 30? internal pullup. 20 in1 monitored input voltage 1. see table 1 for the input voltage threshold. 21 in2 monitored input voltage 2. see table 1 for the input voltage threshold. 22 in3 monitored input voltage 3. see table 1 for the input voltage threshold. 23 in4 monitored input voltage 4. see table 1 for the input voltage threshold. 24 tol threshold tolerance input. connect tol to gnd to select 5% threshold tolerance. connect tol to v cc to select 10% threshold tolerance. ? p e xp osed p ad . e p i s i nter nal l y connected to gn d . c onnect e p to the g r ound p l ane to p r ovi d e a l ow ther m al r esi stance p ath fr om the ic j uncti on to the p c b. d o not use as the el ectr i cal connecti on to gn d . pin description (max16062) downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 10 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ table 1. input-voltage-threshold selector part in1 in2 in3 in4 in5 in6 in7 in8 max16060a 3.3 2.5 adj 1.8 max16060b 3.3 adj adj 1.8 max16060c adj 2.5 adj 1.8 max16060d 3.3 2.5 adj adj max16060e adj adj adj adj max16061a 3.3 2.5 adj 1.8 adj adj max16061b 3.3 adj adj 1.8 adj adj max16061c 3.3 2.5 adj adj adj adj max16061d adj 2.5 adj 1.8 adj adj max16061e adj adj adj adj adj adj max16062a 3.3 2.5 adj 1.8 adj adj adj adj max16062b 3.3 adj adj 1.8 adj adj adj adj max16062c 3.3 2.5 adj adj adj adj adj adj max16062d adj 2.5 adj 1.8 adj adj adj adj max16062e adj adj adj adj adj adj adj adj note: other fixed thresholds may be available. contact factory for availability. downloaded from: http:///
max16060/max16061/max16062 max16060d reference undervoltage lockout v cc in1 out1 resetout2 out3 out4 margin in2in3 in4 tol v cc reset circuit watchdog timer circuit output driver en mr srt wdi timing v cc v cc v cc figure 1. max16060d functional diagram functional diagrams 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 11 downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 12 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ max16061c reference undervoltage lockout v cc in1 out1 resetout2 out3 out6 margin in2in3 in4 tol v cc reset circuit watchdog timer circuit output driver en mr srt wdi timing v cc v cc v cc in5in6 out4out5 figure 2. max16061c functional diagram functional diagrams (continued) downloaded from: http:///
max16060/max16061/max16062 max16062c reference undervoltage lockout v cc in1 margin in2in3 in4 tol v cc reset circuit watchdog timer circuit output driver en mr srt wdi timing v cc v cc in5in6 in7in8 out1 resetout2 out3 out8 v cc out4out5 out6 out7 figure 3. max16062c functional diagram functional diagrams (continued) 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 13 downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ detailed description the max16060/max16061/max16062 are 1% accuratelow-voltage, quad-/hex-/octal-voltage ? supervisors in a small thin qfn package. these devices provide supervisory functions for complex multivoltage systems. the max16060 monitors four voltages; the max16061 monitors six voltages; and the max16062 monitors eight voltages. these supervisors offer independent outputs for each monitored voltage along with a reset output that asserts whenever any of the monitored voltages fall below their respective thresholds or the manual reset input is asserted. the reset output remains asserted for the reset timeout after all voltages are above their respec- tive thresholds and the manual reset input is deassert- ed. the minimum reset timeout is internally set to 140ms or can be adjusted with an external capacitor. all open-drain outputs have internal 30? pullups that eliminate the need for external pullup resistors. however, each output can be driven with an external voltage up to 5.5v. other features offered include a manual reset input, a tolerance pin for selecting 5% or 10% input thresholds, and a margin enable function for deasserting the outputs during margin testing. an additional feature is a watchdog timer that asserts reset when the watchdog timeout period (1.6s typ) is exceeded. the watchdog timer can be disabled byleaving wdi unconnected. applications information undervoltage-detection circuit the open-drain outputs of the max16060/max16061/max16062 can be configured to detect an undervoltage condition. figure 4 shows a configuration where an led turns on when the comparator output is low, indicating an undervoltage condition. these devices can also be used in applications such as sys- tem supervisory monitoring, multivoltage level detection, and v cc bar-graph monitoring (figure 5). tolerance (tol) the max16060/max16061/max16062 feature a pin-selectable threshold tolerance. connect tol to gnd to select 5% threshold tolerance. connect tol to v cc to select 10% threshold tolerance. window detection a window detector circuit uses two inputs in the config-uration shown in figure 6. external resistors set the two threshold voltages of the window detector circuit. external logic gates create the out signal. the window detection width is the difference between the threshold voltages (figure 7). max16060 gnd v cc in1 v1 5vv2 v3 v4 out1 in2in3 in4 out2out3 out4 figure 4. quad undervoltage detector with led indicators max16060 gnd d2 v cc in1 v in (5v) 5v out1 in2in3 in4 out2out3 out4 d1 d3 d4 figure 5. v cc bar-graph monitoring downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 15 adjustable input these devices offer several monitor options withadjustable input thresholds (see table 1). the threshold voltage at each adjustable in_ input is typically 0.394v (tol = gnd) or 0.373v (tol = v cc ). to monitor a volt- age v inth , connect a resistive-divider network to the cir- cuit as shown in figure 8. v inth = v th ((r1/r2) + 1) r1 = r2 ((v inth /v th ) - 1) large resistors can be used to minimize current throughthe external resistors. for greater accuracy, use lower- value resistors. unused inputs connect any unused in_ inputs to a voltage above itsthreshold. out_ outputs the out_ outputs go low when their respective in_inputs drop below their specified thresholds. the output is open drain with a 30? internal pullup to v cc . for many applications, no external pullup resistor is requiredto interface with other logic devices. an external pullup resistor to any voltage from 0 to 5.5v overrides the inter- nal pullup if interfacing to different logic supply voltages. internal circuitry prevents reverse current flow from the external pullup voltage to v cc (figure 9). max16060e gnd v cc in1 5v r2 input r1 out1 in2in3 out in4 out2out3 out4 r4 r3 v th1 = ( 1 + r1 ) ( v th + v th_hys ) r2 v th4 = ( 1 + r3 ) v th r4 figure 6. window detection r1 v inth v th r2 r1 = r2 ( v inth ) v th - 1 figure 8. setting the adjustable input v th v th4 v th1 out out4 out1 figure 7. output response of window detector circuit downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors 16 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ reset output reset asserts low when any of the monitored voltages fall below their respective thresholds or mr is asserted. reset remains asserted for the reset timeout period after all monitored voltages exceed their respectivethresholds and mr is deasserted (see figure 10). this open-drain output has a 30? internal pullup. an externalpullup resistor to any voltage from 0 to 5.5v overrides the internal pullup if interfacing to different logic supply volt- ages. internal circuitry prevents reverse current flow from the external pullup voltage to v cc (figure 9). reset timeout capacitor the reset timeout period can be adjusted to accommo-date a variety of ? applications. adjust the reset time- out period (t rp ) by connecting a capacitor (c srt ) between srt and gnd. calculate the reset timeoutcapacitor as follows: connect srt to v cc for a factory-programmed reset timeout of 140ms (min). manual reset input ( mr ) many ?-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. a logic-low on mr asserts reset low. reset remains asserted while mr is low, and during the reset timeout period (140ms min)after mr returns high. the mr input has an internal 20k pullup resistor to v cc , so it can be left uncon- nected if not used. mr can be driven with ttl or cmos-logic levels, or with open-drain/collector outputs.connect a normally open momentary switch from mr to gnd to create a manual reset function. externaldebounce circuitry is not required. if mr is driven from long cables or if the device is used in a noisy environ-ment, connecting a 0.1? capacitor from mr to gnd provides additional noise immunity. cf tsxi v srt rp srt th srt () () _ = max16060max16061 max16062 gnd v cc gnd reset v cc 5v out_ v cc = 3.3v 100k figure 9. interfacing to a different logic supply voltage in_ 10% 90% 10% 90% reset out_ v th_ t rp t d t d t rd v th_ figure 10. output timing diagram downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 17 margin output disable ( margin ) margin allows system-level testing while power sup- plies are adjusted from their nominal voltages. drivemargin low to force reset and out_ high, regard- less of the voltage at any monitored input. the state ofeach output does not change while margin = gnd. the watchdog timer continues to run when margin is low, and if a timeout occurs, reset will assert t md after margin is deasserted. the margin input is internally pulled up to v cc . leave margin unconnected or connect to v cc if unused. undervoltage lockout (uvlo) the max16060/max16061/max16062 feature a v cc undervoltage lockout (uvlo) that preserves a resetstatus even if v cc falls as low as 1v. the undervoltage lockout circuitry monitors the voltage at v cc . if v cc falls below the uvlo falling threshold (typically 1.735v), reset is asserted and all out_ are asserted low. this eliminates an incorrect reset or out_ output state as v cc drops below the normal v cc operational voltage range of 1.98v to 5.5v.during power-up as v cc rises above 1v, reset is asserted and all out_ are asserted low until v cc exceeds the uvlo threshold. as v cc exceeds the uvlo threshold, all inputs are monitored and the correct outputstate appears at all the outputs. this also ensures that reset and all out_ are in the correct state once v cc reaches the normal v cc operational range. power-supply bypassing in noisy applications, bypass v cc to ground with a 0.1? capacitor as close to the device as possible. theadditional capacitor improves transient immunity. for fast-rising v cc transients, additional capacitance may be required. downloaded from: http:///
max16060/max16061/max16062 1% accurate, quad-/hex-/octal-voltage p supervisors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. pin configurations + 1516 14 13 65 7 in4 gnd 8 in3 out2srt out1 12 in1 4 12 11 9 in2 tol mrout4 out3 v cc max16060 wdi margin 3 10 reset thin qfn (4mm x 4mm) top view + 1920 18 17 76 8 in5 wdi gnd 9 in4 out2margin srt out1 12 in2 45 15 14 12 11 in3 tol out6out5 out4 v cc max16061 in6 out3 3 13 in1 16 10 mr reset thin qfn (4mm x 4mm) top view + marginsrt 2324 22 21 87 9 in6in8 wdi gnd 10 in5 12 in3 456 17 18 16 14 13 in4 tol out7out6 out5 v cc max16062 in7 3 15 in2 20 11 out8 in1 19 12 mr reset thin qfn (4mm x 4mm) top view out2 out1out3 out4 chip information process: bicmos package information for the latest package outline information, go to www.maxim-ic.com/packages . package type package code document no. 16 tqfn t1644-4 21-0139 20 tqfn t2044-3 21-0139 24 tqfn t2444-4 21-0139 downloaded from: http:///

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